Enhancement mode

6m 21s

Enhancement mode Part A

9m 37s

Enhancement mode Part B

11m 17s

Logic design and Analog design

11m 59s

Design Verification and Physical Design

11m 40s

DFT; AMS and Physical Verification Part 1

8m 1s

DFT; AMS and Physical Verification Part 2

6m 5s

Chip design steps

9m 16s

Universal gates; CMOS Part 1

7m 50s

Universal gates; CMOS Part 2

8m 42s

NOR CMOS equivalent

8m 55s

Combinational and sequential circuits full adder example Part 1

9m 3s

Basic gates

12m 2s

Combinational and sequential circuits full adder example Part 2

8m 10s

SR Latch; Tff down counter Part 1

8m 17s

SR Latch; Tff down counter Part 2

4m 34s

Tff; Programmable logic intro Part 1

7m 49s

Tff; Programmable logic intro Part 2

5m 40s

PLA and PAL

7m 31s

FPGA intro and features Part 1

5m 32s

FPGA intro and features Part 2

6m 39s

State machine introduction Part 1

8m 35s

State machine introduction Part 2

5m 44s

State machine example more model Part 1

6m 5s

State machine example more model Part 2

9m 47s

FSM to detect sequences examples Part 1

7m 57s

FSM to detect sequences examples Part 2

7m 45s

End of Digital logic; introduction to Verilog

11m 52s

Verilog features; design styles

12m 56s

Basics; Identifiers in Verilog

10m 37s

Numbers in Verilog

13m 10s

strings; registers; data types Part 1

10m 47s

strings; registers; data types Part 2

9m 7s

Time memories module intro

12m 9s

module structure; Flip flop Verilog code Part 1

7m 49s

module structure; Flip flop Verilog code Part 2

8m 46s

Flip-flop; ripple carry counter Part 1

11m 35s

Flip-flop; ripple carry counter Part 2

12m 10s

Basic gates instantiation

12m 58s

Verilog Operators Part 1

6m 34s

Verilog Operators Part 2

7m 12s

Operators contd

8m 10s

Timing control in Verilog-Delay based

9m 42s

Delay based Intra-assign

9m 36s